1. Field of the Invention
This invention is related to the field of processors and, more particularly, to data reference address checking in processors.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
As computer systems have continued to evolve, 64 bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64 bit address and/or operand sizes.
Unfortunately, the x86 architecture is limited to a maximum 32 bit operand size and 32 bit address size. The operand size refers to the number of bits operated upon by the processor (e.g. the number of bits in a source or destination operand). The address size refers to the number of bits in an address generated by the processor. Thus, processors employing the x86 architecture may not serve the needs of applications which may benefit from 64 bit address or operand sizes.
The x86 architecture defines a segmented address space. With segmentation, the address space is divided into a set of variable sized segments. Segment descriptors are used to describe the segments, including a base address and limit which define the boundaries of the segment.
A processor is described which supports several operating modes. In at least one of the operating modes, a segmented address space is used. In at least one other operating mode, an unsegmented address space is used. In the unsegmented address space, a canonical check applies to addresses. In the segmented address space, a segment limit check applies. In some cases, both a segment limit check and a canonical check applies dependent on the segment used (e.g. either user or table segments). In one example, the processor may include an address generation unit and a load/store unit used to perform data references. The address generation unit may generate an effective address of the data reference and may perform a canonical check on the effective address, generating a first canonical check result. The load/store unit may add the effective address to a segment base address (which may be zero in unsegmented address space modes) to form a linear address and may perform a second canonical check on the linear address, generating a second canonical check result. Additionally, a segment limit check may be performed on the effective address to produce a segment limit check result. An exception circuit selects one or more of the first canonical check result, the second canonical check result, and the segment limit check result to be used to generate an exception indication. The selection is dependent on the operating mode and the segment of the data reference.
The processor may also perform selective truncation of addresses based on the operating mode and the segment. Such truncation may replicate behavior in some operating modes which have an address size smaller than the implemented address space. Furthermore, some embodiments may employ a programmable mechanism for disabling truncation (e.g. a bit in a special purpose register or model specific register). The programmable mechanism, in conjunction with segment base addresses extended to the implemented address size, may be used to perform memory sizing in a mode in which the address size is less than the implemented address size.
Broadly speaking, an apparatus for a processor is contemplated. The apparatus comprises circuitry configured to perform one or more canonical checks for a data reference and a segment limit check on an effective address of the data reference. Additionally, the apparatus includes a first circuit coupled to the circuitry and coupled to receive an indication of an operating mode of the processor and an indication of the segment corresponding to the data reference. The first circuit is configured to select, responsive to the operating mode of the processor and the segment, one or more of: a first result of the segment limit check and a second result of the one or more canonical checks for generating an exception indication for the data reference.
Additionally, an apparatus for a processor is contemplated. The apparatus includes a circuit configured to output an address of a data reference and a control circuit. The circuit is coupled to receive a control input and is configured to output the address either truncated to a predetermined number of bits or not truncated dependent on the control input. The control circuit is configured to generate the control input responsive to a segment of the data reference and an operating mode of the processor.
Moreover, a method is contemplated. An indication in a register is set to a first state which prevents truncation of data reference addresses. A plurality of data references are performed to determine a size of memory included in a system. The indication is set to a second state which allows truncation of data reference addresses.